The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (AISCs), and other high-speed integrated circuits (ICs). The present invention provides low dielectric constant (i.e., low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and reduced fabrication cost. Moreover, the structures of the present invention have a lower effective dielectric constant and improved control over metal line resistance as compared with prior art interconnect structures.
Many low-k (on the order of about 3.5 or less) plus Cu interconnect structures of the dual damascene-type are known; See, for example, R. D. Goldblatt, et al., xe2x80x9cA High Performance 0.13 xcexcm Copper BEOL Technology with Low-K Dielectricxe2x80x9d, Proceedings of the International Interconnect Technology Conference, IEEE Electron Devices Society, Jun. 5-7, 2000, pgs 261-263. Such prior art interconnect structures include inorganic as well as organic dielectric materials as the interlevel or intralevel dielectric. It is widely accepted that dual-damascene structures are lower cost than single damascene or subtractive metal structures.
Typically, there are four essential problems associated with prior art dual damascene interconnect structures which include the following:
(i) Poor control over Cu line thickness (i.e., trench depth) and resistivity.
(ii) High coefficient of thermal expansion (CTE) of low-k dielectrics, which may eventually lead to failure during thermal cycling.
(iii) The inability of low-k dielectrics to survive chemical-mechanical polishing (CMP).
(iv) Increased cost to fabricate the structures.
During fabrication of prior art interconnect structures, the depth of the trenches that become the metal line conductors (after metal fill and CMP) is often poorly controlled, and the trench bottom has a rough surface. This effect is exacerbated when performing reactive-ion etching (RIE) on porous dielectrics. A timed reactive-ion etching (RIE) process is typically used to etch the trenches, with time controlling the trench depth. Variations in the etch rate with feature size (trench width) from day to day, and across the wafer, lead to large variations in the trench depth which, in turn, leads to large variations in the metal conductor resistance. Roughness at the trench bottom leads to higher capacitance, leaky electron current between metal levels, cross-talk, noise, power dissipation and ultimately, to poorer device performance and poorer reliability.
Common solutions to the aforementioned problems add extra processing steps, including deposition of a discrete etch stop layer in a separate plasma-enhanced chemical vapor deposition (PECVD) tool, thus raising the cost of fabricating the desired low-k plus Cu interconnect structure.
Additionally, low-k dielectrics plus Cu interconnect structures of the dual damascene-type fail during thermal cycling tests due to a high-CTE of the dielectric surrounding the vias. Moreover, commonly used porous low-k dielectrics do not survive CMP. Instead, prior art porous low-k dielectrics tend to delaminate and be removed during the CMP process. Furthermore, prior art etch stop layers are made from vacuum-based PECVD deposition tools that are costly to purchase and maintain. p In view of the above problems in the prior art, there is a continued need for providing new and improved low-k dielectrics which can be used in interconnect structures of the dual damascene-type that overcome the drawbacks mentioned above.
One object of the present invention is to provide an interconnect structure of the dual damascene-type comprising a multilayer low-k dielectric stack and metal conductor in which precise and uniform control over the metal conductor resistance is obtained.
Another object of the present invention is to provide an interconnect structure in which a spun-on buried etch stop layer is provided between spun-on dielectrics of a multilayer low-k dielectric stack.
A further object of the present invention is to provide an interconnect structure in which the buried etch stop layer of a multilayer low-k dielectric stack will react and form covalent bonds between a bottom spun-on low-k dielectric and a top spun-on low-k dielectric of the multilayer dielectric stack.
An even further object of the present invention is to provide an interconnect structure in which the buried etch stop layer also functions to improve the adhesion between a bottom spun-on low-k dielectric and a top spun-on low-k dielectric of the multilayer dielectric stack, thereby eliminating the need of an additional adhesion promoter.
A yet further object of the present invention is to provide precise control over the metal conductor resistance of an interconnect structure without adding additional processing steps and cost.
An additional object of the present invention is to provide an interconnect structure which comprises a multilayer of low-k dielectrics which are formed by spin coating thereby reducing the use of costly vacuum-based deposition tools.
These and other objects and advantages are achieved in the present invention by utilizing a buried etch stop layer with a multilayer low-k dielectric stack which is capable of chemically bonding to both the bottom and top low-k spun-on dielectric layers through incorporation of a functional organosilane containing groups that are capable of covalently bonding with the dielectrics of the multilayer low-k dielectric stack.
Specifically, the interconnect structure of the present invention comprises:
a substrate having a patterned multilayer of spun-on dielectrics formed on a surface thereof, said patterned multilayer of spun-on dielectrics comprising a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein said bottom and top low-k dielectrics have a first composition, and said buried etch stop layer has a second composition which is different from said first composition and said buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics;
a polish stop layer formed on said patterned multilayer of spun-on dielectrics; and
metal conductive regions formed within said patterned multilayer of spun-on dielectrics.
The present invention also provides a multilayer spun-on dielectric which comprises a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein said bottom and top low-k dielectrics have a first composition, and said buried etch stop layer has a second composition which is different from said first composition and said buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics.
Another aspect of the present invention comprises a method of forming the aforementioned interconnect structure. Specifically, the inventive method comprises the steps of:
(a) forming a multilayer of spun-on dielectrics on a surface of a substrate, said multilayer of spun-on dielectrics comprising a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein said bottom and top low-k dielectrics have a first composition, and said buried etch stop layer has a second composition which is different from said first composition and said buried etch stop layer is capable of covalently bonding to said top and bottom low-k dielectrics in a subsequent curing step;
(b) curing said multilayer of spun-on dielectrics, wherein during said curing said buried etch stop layer covalently bonds to said top and bottom low-k dielectrics, while undergoing crosslinking;
(c) forming a hard mask on said cured multilayer of spun-on dielectrics, said hard mask including at least a polish stop layer;
(d) forming an opening in said hard mask so as to expose a portion of said multilayer of spun-on dielectrics;
(e) forming a trench in said exposed portion of said multilayer of spun-on dielectrics;
(f) filling said trench with at least a conductive metal; and
(g) planarizing said conductive metal stopping on said polish stop layer.
It is noted that the method described above relates to an embodiment of the present invention wherein the hard mask is formed by deposition processing other than spin-on coating. When the hard mask is formed by spin-on coating, the method of the present invention includes the steps of:
(a) forming a multilayer of spun-on dielectrics on a surface of a substrate, said multilayer of spun-on dielectrics comprising a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein said bottom and top low-k dielectrics have a first composition, and said buried etch stop layer has a second composition which is different from said first composition and said buried etch stop layer is capable of covalently bonding to said top and bottom low-k dielectrics in a subsequent curing step;
(b) forming a hard mask on said multilayer of spun-on dielectrics, said hard mask including at least a polish stop layer;
(c) curing said hard mask and said multilayer of spun-on dielectrics, wherein during said curing said buried etch stop layer covalently bonds to said top and bottom low-k dielectrics, while undergoing crosslinking;
(d) forming an opening in said hard mask so as to expose a portion of said multilayer of spun-on dielectrics;
(e) forming a trench in said exposed portion of said multilayer of spun-on dielectrics;
(f) filling said trench with at least a conductive metal; and
(g) planarizing said conductive metal stopping on said polish stop layer.
It is noted that the above method is preferred over the previously mentioned method since a single spin coating tool can be used for forming the various layers of the multilayer of spun-on dielectrics and the hard mask.